Advanced Ultra-low Power (AUP)

Advanced Ultra-low Power (AUP)

Introduction
Products
More Info

Introduction

Key Features:

Very low dynamic power dissipation (C_PD)
Wide V_CC from 0.8V to 3.6V
Schmitt trigger inputs provide high noise immunity
Superior ESD protection
Wide operating temperature of -40°C to +125°C
T_PD of 3.2ns and I_OL of 2.2mA at 1.8V V_CC
Available initially in single/dual gate functions
PicoGate and MicroPak packaging

Products

All and New

All AUP Products
New AUP Products

Functions

D-Type Flip-Flops

Gates

AND Gates
NAND Gates
OR Gates
NOR Gates
EXCLUSIVE-OR Gates
OR-AND Gates
Configurable Multiple Function Gates

More Information

Family Information

AUP Family Overview

	Easy test and evaluation of the 74AUP1Z04 NXP AUP1Z04 Evaluation board © June 2010; English; Ordering Code: 9397 750 16907
	Advanced, ultra-low-power CMOS logic NXP ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx © September 2009; English; Ordering Code: 9397 750 16800

Packaging Information

MicroPak XSON Packaging
PicoGate Packaging

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