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Dual-gate LVC products
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Dual-Gate LVC Products
| 74LVC2G00 | 3.3V Dual 2-Input NAND Gate | |
| 74LVC2G02 | 3.3V Dual 2-Input NOR Gate | |
| 74LVC2G02-Q100 | 3.3V Dual 2-Input NOR Gate; AEC Q100 (Grade 1) qualified  | |
| 74LVC2G04 | 3.3V Dual Inverter | |
| 74LVC2GU04 | 3.3V Dual Inverter (Unbuffered) | |
| 74LVC2GU04-Q100 | 3.3V dual inverter (unbuffered); AEC Q100 (Grade 1) qualified | |
| 74LVC2G06 | 3.3V dual inverter with open-drain outputs | |
| 74LVC2G06-Q100 | 3.3V dual inverter with open-drain outputs; AEC Q100 (Grade 1) qualified | |
| 74LVC2G07 | 3.3V dual buffer with open-drain outputs | |
| 74LVC2G08 | 3.3V Dual 2-Input AND Gate | |
| 74LVC2G14 | 3.3V Dual Schmitt-Trigger Inverter | |
| 74LVC2G17 | 3.3V Dual Schmitt-Trigger Buffer | |
| 74LVC2G17-Q100 | 3.3V dual schmitt-trigger buffer; AEC Q100 (Grade 1) qualified | |
| 74LVC2G32 | 3.3V Dual 2-Input OR Gate | |
| 74LVC2G34 | 3.3V dual buffer | |
| 74LVC2G34-Q100 | 3.3V dual buffer; AEC Q100 (Grade 1) qualified | |
| 74LVC2G38 | 3.3V dual 2-input NAND gate with open-drain outputs | |
| 74LVC2T45 | 3.3V dual-bit, dual-supply voltage level translating transceiver (3-state) | |
| 74LVC2T45-Q100 | 3.3V dual-bit, dual-supply voltage level translating transceiver (3-state); AEC Q100 (Grade 1) qualified | |
| 74LVCH2T45 | 3.3V dual-bit, dual-supply voltage level translating transceiver with bus hold (3-state) | |
| 74LVCH2T45-Q100 | 3.3V dual-bit, dual-supply voltage level translating transceiver with bus hold (3-state); AEC Q100 (Grade 1) qualified | |
| 74LVC2G53 | Single 3.3V single-pole, double-throw, center-off analog switch (SPDT-CO) | |
| 74LVC2G66 | Dual 3.3V single-pole, single-throw bilateral analog switch (2 X SPST-NO) | |
| 74LVC2G66-Q100 | Dual 3.3V single-pole, single-throw bilateral analog switch (2 X SPST-NO); AEC Q100 (Grade 1) qualified | |
| 74LVCV2G66 | Dual 3.3V overvoltage-tolerant, single-pole, single-throw analog switch (2 X SPST-NO) | |
| 74LVC2G74 | 3.3V single D-type flip-flop with set and reset; positive edge trigger | |
| 74LVC2G74-Q100 | 3.3V single D-type flip-flop with set and reset; positive edge trigger; AEC Q100 (Grade 1) qualified | |
| 74LVC2G86 | 3.3V Dual 2-Input EXCLUSIVE-OR Gate | |
| 74LVC2G125 | 3.3V Dual Bus Buffer/Line Driver (3-State) | |
| 74LVC2G126 | 3.3V Dual Bus Buffer/Line Driver (3-State) | |
| 74LVC2G240 | 3.3V Dual Buffer/Line Driver with 5V-Tolerant Inputs/Outputs; Inverting (3-State) | |
| 74LVC2G241 | 3.3V Dual Buffer/Line Driver with 5V-Tolerant Inputs/Outputs (3-State) | |
| 74LVC2G241-Q100 | 3.3V Dual Buffer/Line Driver with 5V-Tolerant Inputs/Outputs (3-State); AEC Q100 (Grade 1) qualified | |
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