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PCI Express x1 PHY single-lane transceivers

PCI Express x1 PHY single-lane transceivers

Introduction
For applications that use an ASIC or a low-cost FPGA to implement the MAC portion of the PCI Express protocol, NXP Semiconductors offers our PX1011 2.5-Gbps PCI Express PHY transceivers with 8-bit data PXPIPE interfaces. Available in very small, leaded and lead-free LFBGA-81 packages that measure only 9 x 9 x 1.05 mm, they offer features that ease layout, improve performance, and increase design flexibility.
NXP Semiconductors is the first discrete PCI Express PHY vendor to pass the PCI-SIG compliance tests. NXP Semiconductors has worked with multiple partners to perform comprehensive tests in multiple PC systems to ensure interoperability, compliance, and excellent throughput.
Fast, low-risk digital ASIC designs
Our PX1011 products makes ASIC development faster and less risky. By isolating the mixed-signal PHY functions in an external transceiver, they let the ASIC's digital functions migrate to the latest process technologies without impacting complex PHY operations.
Increased efficiency of low-cost FPGA designs
Low-cost, high-density FPGAs don't typically offer an on-chip PHY or SERDES. PX1011 products let designers use an inexpensive FPGA to create low-cost, flexible PCI Express applications that have customer-specific functions coded into the FPGA. The result is greater differentiation in a format that is easily scalable to high-volume, consumer-oriented applications.
Tiny package optimized for PCB layout
Our PX1011 PHYs come in the industry's smallest package, the LFBGA-81. Despite its tiny size, we have optimized the ease of layout by having 2 signal rings, thus requiring only two signal layers in the PCB design.
Features
  • PCI Express v1.0a compliant
  • Passes PCI Express v1.1 informational jitter tests from PCI-SIG
  • Suitable for ExpressCard applications
  • One x1 physical lane
  • Transmit or receive at 2.5Gbps
  • Better than 1x10-12 Bit Error Rate (BER)
  • NXP PXPIPE (8-bit, 250-MHz) PHY-MAC interface
  • FPGA-compatible SSTL2 signaling
  • L0, L0s, L1 power management modes; partial support for L2, L3
  • Leaded or lead-free LFBGA-81 package (9 x 9 x 1.05 mm)
Products

Literature

PCI Express PHY
NXP x1 PHY single-lane transceiver PX1011
© November 2007; English; Ordering Code: 9397 750 16134

PCIe x1 PHY Single-Lane Transceivers

PX1011BPCI Express stand-alone X1 PHY with improved transmitter jitter and supply range

Ordering Information

The PCIe x1 PHY single-lane transceivers can be purchased from authorized distributors:

PCI Express IP Cores

The Xilinx Spartan-3/3E FPGA has high-speed I/O capability and supports the 8-bit, 250-MHz PXPIPE interface used in the PX1011 products. Xilinx also supports our PX1011 products with their LogiCORE PCIe PIPE Endpoint IP.
Altera's Cyclone-II FPGA supports the PXPIPE interface with their PCI Express MegaCore.
PLDA's PCI Express IP core supports the PX1011 products on both the Altera Cyclone II and Xilinx Spartan-3/3E FPGAs.
For more information about the IP vendors that support the NXP PXPIPE interface, please see our NXP NXP PXPIPE PHY/MAC Interface FAQ.
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